Main Responsibilities:

  • Responsible for design verification of mixed signal IC’s in a digital / mixed signal design environment
  • Proficiency in System Verilog including writing checkers and assertions, customizing constraints, getting functional coverage collection using cover groups, etc.
  • Technical and team leadership – both within the internal project DV team (digital and mixed-signal verification), but also directly supporting customers during project reviews or status calls
  • Primary focus is on mixed signal design verification, but proficiency with digital design verification (including UVM) is an plus
  • Creation and validation of System Verilog models for mixed signal circuit blocks
  • Creation of test benches and automated verification simulations
  • Experience running both analog (SPICE) and digital simulators is a strong advantage
  • Performing block level and top level design verification
  • Generation of relevant documentation (DV Plan, DV execution plan, customer reviews etc.)
  • Experience on electrical checks, static and dynamic, is a plus.

Desired Educational Background:

  • Master’s degree in Electrical / Computer Engineering with 10 years (senior) or 5 years (staff) of experience in Design Verification
  • Experience (senior) or exposure (staff) to project or technology leadership role
  • System Verilog / UVM based mixed signal DV (Design Verification) experience
  • Collaborative and respectful team player with mentoring skills, and passionate about achieving team goals
  • Excellent communication skills (both oral and written) are required, as real time customer level technical interface and design / team leadership is necessary.
  • Experience with relevant CAD tools